Hybrid Cellular Automata-Based Pseudo Random Sequence Generator for BIST Implementation

The technique of Test pattern generation plays a key role in Built-In-Self-Test(BIST) architecture implementation. Main problem with any test pattern generator is to produce extended, random path succession which is applied to Circuit Under Test(CUT) for detecting faults. As real long numbers can be acquired as a part of physical developments only, these are complex to be employed inactual applications. Therefore, pseudorandom numbers are generated by artificial design patterns. In this paper we present a variation on a built-in-self-test (BIST) technique, which is based upon a pseudo random number generator derived from a onedimensional linear hybrid cellular automata (LHCA) array. Certain types of circuit faults are undetectable using the correlated bit streams produced by linear-feedback-shift-register (LFSR). In addition it is noted that CA implementations exhibit data compression properties similar to the LFSR. It is also possible that some of the analysis of pseudorandom testing may be more directly applicable to LHCA-based pseudorandom testing than to LFSR-based schemes. In the last two decades, researchers devoted many efforts to reduce the average power consumption in VLSI systems during normal operation mode, while power consumption during test operation mode was usually neglected. However, during test application circuits are subject to an activity level higher than the normal one: the extra power consumption due to test application may thus rise severe hazards to the circuit reliability. Moreover, it can dramatically shorten battery life when periodic testing of battery-powered systems is considered. In this paper we propose an algorithm to design a Test Pattern Generator based on Hybrid Cellular Automata for testing combinational circuits that effectively reduces power consumption.